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FPGA
2012
ACM
337views FPGA» more  FPGA 2012»
11 years 11 months ago
Accelerator compiler for the VENICE vector processor
Zhiduo Liu, Aaron Severance, Satnam Singh, Guy G. ...
FPGA
2012
ACM
285views FPGA» more  FPGA 2012»
11 years 11 months ago
Optimizing SDRAM bandwidth for custom FPGA loop accelerators
Memory bandwidth is critical to achieving high performance in many FPGA applications. The bandwidth of SDRAM memories is, however, highly dependent upon the order in which address...
Samuel Bayliss, George A. Constantinides
VLSI
2012
Springer
11 years 11 months ago
A Signature-Based Power Model for MPSoC on FPGA
e technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used instruction-set sim...
Roberta Piscitelli, Andy D. Pimentel
ASPDAC
2012
ACM
253views Hardware» more  ASPDAC 2012»
11 years 11 months ago
An integrated and automated memory optimization flow for FPGA behavioral synthesis
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong
FPGA
2012
ACM
300views FPGA» more  FPGA 2012»
11 years 11 months ago
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs
In floating-point datapaths synthesized on FPGAs, the shifters that perform mantissa alignment and normalization consume a disproportionate number of LUTs. Shifters are implemente...
Yehdhih Ould Mohammed Moctar, Nithin George, Hadi ...