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HPCA
1999
IEEE
13 years 9 months ago
Impulse: Building a Smarter Memory Controller
Impulse is a new memory system architecture that adds two important features to a traditional memory controller. First, Impulse supports application-specific optimizations through...
John B. Carter, Wilson C. Hsieh, Leigh Stoller, Ma...
HPCA
1999
IEEE
13 years 9 months ago
Using Lamport Clocks to Reason about Relaxed Memory Models
Cache coherence protocols of current shared-memory multiprocessors are difficult to verify. Our previous work proposed an extension of Lamport's logical clocks for showing th...
Anne Condon, Mark D. Hill, Manoj Plakal, Daniel J....
HPCA
1999
IEEE
13 years 9 months ago
Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance
In general-purpose microprocessors, recent trends have pushed towards 64-bit word widths, primarily to accommodate the large addressing needs of some programs. Many integer proble...
David Brooks, Margaret Martonosi
HPCA
1999
IEEE
13 years 9 months ago
WildFire: A Scalable Path for SMPs
Researchers have searched for scalable alternatives to the symmetric multiprocessor (SMP) architecture since it was first introduced in 1982. This paper introduces an alternative ...
Erik Hagersten, Michael Koster
HPCA
1999
IEEE
13 years 9 months ago
Limits to the Performance of Software Shared Memory: A Layered Approach
Much research has been done in fast communication on clusters and in protocols for supporting software shared memory across them. However, the end performance of applications that...
Angelos Bilas, Dongming Jiang, Yuanyuan Zhou, Jasw...