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HPCA
2000
IEEE
11 years 2 months ago
Cache-Efficient Matrix Transposition
Siddhartha Chatterjee, Sandeep Sen
ISCA
2003
IEEE
89views Hardware» more  ISCA 2003»
11 years 3 months ago
MisSPECulation: Partial and Misleading Use of SPEC CPU2000 in Computer Architecture Conferences
A majority of the papers published in leading computer architecture conferences use SPEC CPU2000, or its predecessor SPEC CPU95, which has become the de facto standard for measuri...
Daniel Citron
HPCA
2000
IEEE
11 years 3 months ago
Decoupled Value Prediction on Trace Processors
Value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction, and executes speculatively its data-dependent instructions based on ...
Sang Jeong Lee, Yuan Wang, Pen-Chung Yew
HPCA
2000
IEEE
11 years 3 months ago
PowerMANNA: A Parallel Architecture Based on the PowerPC MPC620
The paper presents PowerMANNA - a distributed-memory parallel computer system based on the 64-Bit PowerPC processor MPC620. The PowerMANNA node architecture supports all the sophi...
Peter M. Behr, S. Pletner, Angela C. Sodan
HPCA
2001
IEEE
11 years 11 months ago
Performance of Hardware Compressed Main Memory
A new memory subsystem called Memory Expansion Technology (MXT) has been built for compressing main memory contents. MXT effectively doubles the physically available memory. This ...
Bülent Abali, Dan E. Poff, Hubertus Franke, T...
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