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HPCA
2000
IEEE
13 years 9 months ago
2000
IEEE
We consider a variety of dynamic, hardware-based methods for exploiting load/store parallelism, including mechanisms that use memory dependence speculation. While previous work ha...
HPCA
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper describes a new instruction-supply mechanism, called the eXtended Block Cache (XBC). The goal of the XBC is to improve on the Trace Cache (TC) hit rate, while providing...
HPCA
2000
IEEE
13 years 9 months ago
2000
IEEE
Processor architectures with tens to hundreds of arithmetic units are emerging to handle media processing applications. These applications, such as image coding, image synthesis, ...
HPCA
2000
IEEE
13 years 9 months ago
2000
IEEE
We are attacking the memory bottleneck by building a “smart” memory controller that improves effective memory bandwidth, bus utilization, and cache efficiency by letting appl...
HPCA
2008
IEEE
14 years 5 months ago
2008
IEEE
A microprocessor's performance is fundamentally limited by the rate at which it can resolve branch mispredictions. Control independence (CI) architectures look for useful con...