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HPCA
2003
IEEE
14 years 5 months ago
Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors
Thread-level speculation provides architectural support to aggressively run hard-to-analyze code in parallel. As speculative tasks run concurrently, they generate unsafe or specul...
María Jesús Garzarán, Milos P...
HPCA
2003
IEEE
14 years 5 months ago
Dynamic Data Dependence Tracking and its Application to Branch Prediction
To continue to improve processor performance, microarchitects seek to increase the effective instruction level parallelism (ILP) that can be exploited in applications. A fundament...
Lei Chen, Steve Dropsho, David H. Albonesi
HPCA
2003
IEEE
14 years 5 months ago
Exploring the VLSI Scalability of Stream Processors
Stream processors are high-performance programmable processors optimized to run media applications. Recent work has shown these processors to be more area- and energy-efficient th...
Brucek Khailany, William J. Dally, Scott Rixner, U...
HPCA
2003
IEEE
14 years 5 months ago
Evaluating the Impact of Communication Architecture on the Performability of Cluster-Based Services
We consider the impact of different communication architectures on the performability (performance + availability) of cluster-based servers. In particular, we use a combination of ...
Kiran Nagaraja, Neeraj Krishnan, Ricardo Bianchini...
HPCA
2003
IEEE
14 years 5 months ago
Deterministic Clock Gating for Microprocessor Power Reduction
With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Pipeline ba...
Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykuma...