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HPCA
2007
IEEE
13 years 11 months ago
2007
IEEE
The significant speed-gap between processor and memory and the limited chip memory bandwidth make last-level cache performance crucial for future chip multiprocessors. To use the...
HPCA
2007
IEEE
14 years 4 months ago
2007
IEEE
We apply a scalable approach for practical, comprehensive design space evaluation and optimization. This approach combines design space sampling and statistical inference to ident...
HPCA
2007
IEEE
14 years 4 months ago
2007
IEEE
A thread executing on a simultaneous multithreading (SMT) processor that experiences a long-latency load will eventually stall while holding execution resources. Existing long-lat...
HPCA
2007
IEEE
13 years 11 months ago
2007
IEEE
To provide high dependability in a multithreaded system despite hardware faults, the system must detect and correct errors in its shared memory system. Recent research has explore...
HPCA
2007
IEEE
14 years 4 months ago
2007
IEEE
Utilizing the nonuniform latencies of SDRAM devices, access reordering mechanisms alter the sequence of main memory access streams to reduce the observed access latency. Using a r...