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HPCA
2011
IEEE
12 years 7 months ago
Relaxing non-volatility for fast and energy-efficient STT-RAM caches
Clinton Wills Smullen IV, Vidyabhushan Mohan, Anur...
HPCA
2011
IEEE
12 years 7 months ago
Architectural framework for supporting operating system survivability
The ever increasing size and complexity of Operating System (OS) kernel code bring an inevitable increase in the number of security vulnerabilities that can be exploited by attack...
Xiaowei Jiang, Yan Solihin
HPCA
2011
IEEE
12 years 7 months ago
CloudCache: Expanding and shrinking private caches
The number of cores in a single chip multiprocessor is expected to grow in coming years. Likewise, aggregate on-chip cache capacity is increasing fast and its effective utilizatio...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
HPCA
2011
IEEE
12 years 7 months ago
Bloom Filter Guided Transaction Scheduling
Contention management is an important design component to a transactional memory system. Without effective contention management to ensure forward progress, a transactional memory...
Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mu...
HPCA
2011
IEEE
12 years 7 months ago
Shared last-level TLBs for chip multiprocessors
Translation Lookaside Buffers (TLBs) are critical to processor performance. Much past research has addressed uniprocessor TLBs, lowering access times and miss rates. However, as c...
Abhishek Bhattacharjee, Daniel Lustig, Margaret Ma...