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ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
In this paper we present an enhanced design flow model that increases the capabilities of a CAD framework to support design activities on hierarchical multi-view design descriptio...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
We examine the implications of a new hazard-free combinational logic synthesis method [8], which generates multiplexor trees from binary decision diagrams (BDDs) -- representation...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
We present a new min-cut based placement algorithm for large scale sea-of-gates arrays. In the past all such algorithms used a xed cut line sequence that is determined before min...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
A simple extension of the critical path method is presented which allows more accurate optimization of circuits with level-sensitive latches. The extended formulation provides a s...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...