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iccad 2000
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Exploring Performance Tradeoffs for Clustered VLIW ASIPs
13 years 9 months ago
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Margarida F. Jacome, Gustavo de Veciana, Viktor S....
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UST/DME: A Clock Tree Router for General Skew Constraints
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cobweb.ecn.purdue.edu
Chung-Wen Albert Tsao, Cheng-Kok Koh
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How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K
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Anirudh Devgan, Hao Ji, Wayne Wei-Ming Dai
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Wire Reconnections Based on Implication Flow Graph
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cad63.cs.nthu.edu.tw
Shih-Chieh Chang, Zhong-Zhen Wu, He-Zhe Yu
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DAISY: A Simulation-Based High-Level Synthesis Tool for Delta-Sigma Modulators
13 years 9 months ago
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Kenneth Francken, Peter J. Vancorenland, Georges G...
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