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ICCAD
2010
IEEE
13 years 2 months ago
2010
IEEE
In Double Patterning Lithography (DPL), conflict and stitch minimization are two main challenges. Post-routing mask decomposition algorithms [1
ICCAD
2010
IEEE
13 years 2 months ago
2010
IEEE
Clock networks contribute a significant fraction of dynamic power and can be a limiting factor in high-performance CPUs and SoCs. The need for multi-objective optimization over a l...
ICCAD
2010
IEEE
13 years 2 months ago
2010
IEEE
Craig Interpolation is a state-of-the-art technique for logic synthesis and verification, based on Boolean Satisfiability (SAT). Leveraging the efficacy of SAT algorithms, Craig In...
ICCAD
2010
IEEE
13 years 1 months ago
2010
IEEE
Global Routing has been a traditional EDA problem. It has congestion elimination as the first and foremost priority. Despite of the recent development for popular rip-up and rerout...
ICCAD
2010
IEEE
13 years 2 months ago
2010
IEEE
This paper is concerned with finding timing-independent false paths that cannot be sensitized under any signal arrival time condition in integrated circuits. Existing techniques r...