3D stacked circuits reduce communication delay in multicore system-on-chips (SoCs) and enable heterogeneous integration of cores, memories, sensors, and RF devices. However, vertic...
Mohamed M. Sabry, Ayse Kivilcim Coskun, David Atie...
In this paper, we propose a new technique, referred to as MultiWafer Virtual Probe (MVP) to efficiently model wafer-level spatial variations for nanoscale integrated circuits. Tow...
Wangyang Zhang, Xin Li, Emrah Acar, Frank Liu, Rob...
In 3D integrated circuits through silicon vias (TSVs) are used to connect different dies stacked on top of each other. These TSV occupy silicon area and have significantly larger a...
Mohit Pathak, Young-Joon Lee, Thomas Moon, Sung Ky...
Abstract--We present a methodology for implementing digital signal processing (DSP) operations such as filtering with biomolecular reactions. From a DSP specification, we demonstra...
Hua Jiang, Aleksandra P. Kharam, Marc D. Riedel, K...
1In this paper, we will present an effective layout method for analog circuits. We consider symmetry constraint, common centroid constraint, device merging and device clustering du...
Linfu Xiao, Evangeline F. Y. Young, Xiaoyong He, K...