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ICCD
2006
IEEE
113views Hardware» more  ICCD 2006»
14 years 2 months ago
A theory of Error-Rate Testing
— We have entered an era where chip yields are decreasing with scaling. A new concept called intelligible testing has been previously proposed with the goal of reversing this tre...
Shideh Shahidi, Sandeep Gupta
ICCD
2006
IEEE
148views Hardware» more  ICCD 2006»
14 years 2 months ago
Trends and Future Directions in Nano Structure Based Computing and Fabrication
— As silicon CMOS devices are scaled down into the nanoscale regime, new challenges at both the device and system level are arising. While some of these challenges will be overco...
R. Iris Bahar
ICCD
2006
IEEE
104views Hardware» more  ICCD 2006»
14 years 2 months ago
Guiding Architectural SRAM Models
— Caches, block memories, predictors, state tables, and other forms of on-chip memory are continuing to consume a greater portion of processor designs with each passing year. Mak...
Banit Agrawal, Timothy Sherwood
ICCD
2006
IEEE
117views Hardware» more  ICCD 2006»
14 years 2 months ago
Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses
— The influence of interconnects on processor performance and cost is becoming increasingly pronounced with technology scaling. In this paper, we present a fast compression sche...
Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Maha...
ICCD
2006
IEEE
97views Hardware» more  ICCD 2006»
14 years 2 months ago
Pesticide: Using SMT Processors to Improve Performance of Pointer Bug Detection
Pointer bugs associated with dynamically-allocated objects resulting in out-of-bounds memory access are an important class of software bugs. Because such bugs cannot be detected e...
Jin-Yi Wang, Yen-Shiang Shue, T. N. Vijaykumar, Sa...