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ICPP
1991
IEEE
13 years 8 months ago
B-SYS: A 470-Processor Programmable Systolic Array
This paper presents an architecture for programmable systolic arrays that provides simple and e cient systolic communication. The Brown Systolic Array is a linear implementation o...
Richard Hughey, Daniel P. Lopresti
ICPP
1991
IEEE
13 years 8 months ago
Cache Coherence on a Slotted Ring
-- The Express Ring is a new architecture under investigation at the University of Southern California. Its main goal is to demonstrate that a slotted unidirectional ring with very...
Luiz André Barroso, Michel Dubois
ICPP
1991
IEEE
13 years 8 months ago
Automatic Parallel Program Generation and Optimization from Data Decompositions
Data decomposition is probably the most successful method for generating parallel programs. In this paper a general framework is described for the automatic generation of parallel...
Edwin M. R. M. Paalvast, Henk J. Sips, Arjan J. C....
ICPP
1991
IEEE
13 years 8 months ago
Two Techniques to Enhance the Performance of Memory Consistency Models
The memory consistency model supported by a multiprocessor directly affects its performance. Thus, several attempts have been made to relax the consistency models to allow for mor...
Kourosh Gharachorloo, Anoop Gupta, John L. Henness...
ICPP
1991
IEEE
13 years 8 months ago
Emulation of a PRAM on Leveled Networks
There is an interesting class of ICNs, which includes the star graph and the n-way shuffle, for which the network diameter is sub-logarithmic in the network size. This paper prese...
Michael A. Palis, Sanguthevar Rajasekaran, David S...