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APCSAC
2001
IEEE
13 years 9 months ago
Exploiting Java Instruction/Thread Level Parallelism with Horizontal Multithreading
Java bytecodes can be executed with the following three methods: a Java interpretor running on a particular machine interprets bytecodes; a Just-In-Time (JIT) compiler translates ...
Kenji Watanabe, Wanming Chu, Yamin Li
LCTRTS
2001
Springer
13 years 9 months ago
ILP-based Instruction Scheduling for IA-64
The IA-64 architecture has been designed as a synthesis of VLIW and superscalar design principles. It incorporates typical functionality known from embedded processors as multiply...
Daniel Kästner, Sebastian Winkel
CASES
2001
ACM
13 years 9 months ago
Storage allocation for embedded processors
In an embedded system, it is common to have several memory areas with different properties, such as access time and size. An access to a specific memory area is usually restricted...
Jan Sjödin, Carl von Platen
HPCA
2001
IEEE
14 years 5 months ago
Differential FCM: Increasing Value Prediction Accuracy by Improving Table Usage Efficiency
Value prediction is a relatively new technique to increase the Instruction Level Parallelism (ILP) in future microprocessors. An important problem when designing a value predictor...
Bart Goeman, Hans Vandierendonck, Koenraad De Boss...
IWDC
2001
Springer
114views Communications» more  IWDC 2001»
13 years 9 months ago
A Protection-Based Approach to QoS in Packet over Fiber Networks
We propose a novel approach to Quality of Service, intended for IP over SONET (or IP over WDM) networks, that offers end-users the choice between two service classes defined acco...
Patrick Thiran, Nina Taft, Christophe Diot, Hui Za...