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IOLTS
2000
IEEE
13 years 9 months ago
2000
IEEE
We propose a procedure for self-testing of an FPGA programmed to implement a user-defined function. The procedure is intended to improve the detectability of FPGA delay faults. Th...
IOLTS
2000
IEEE
13 years 9 months ago
2000
IEEE
In this paper, we introduce an efficient technique for checkpointing multithreaded applications. Our approach makes use of processes constructed around the ARMOR (Adaptive Reconfi...
IOLTS
2000
IEEE
13 years 9 months ago
2000
IEEE
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...