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ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
11 years 8 months ago
BlockChop: Dynamic squash elimination for hybrid processor architecture
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
Jason Mars, Naveen Kumar
ISCA
2012
IEEE
208views Hardware» more  ISCA 2012»
11 years 8 months ago
Harmony: Collection and analysis of parallel block vectors
Efficient execution of well-parallelized applications is central to performance in the multicore era. Program analysis tools support the hardware and software sides of this effor...
Melanie Kambadur, Kui Tang, Martha A. Kim
ISCA
2012
IEEE
212views Hardware» more  ISCA 2012»
11 years 8 months ago
TimeWarp: Rethinking timekeeping and performance monitoring mechanisms to mitigate side-channel attacks
Over the past two decades, several microarchitectural side channels have been exploited to create sophisticated security attacks. Solutions to this problem have mainly focused on ...
Robert Martin, John Demme, Simha Sethumadhavan
ISCA
2012
IEEE
320views Hardware» more  ISCA 2012»
11 years 8 months ago
Viper: Virtual pipelines for enhanced reliability
The reliability of future processors is threatened by decreasing transistor robustness. Current architectures focus on delivering high performance at low cost; lifetime device rel...
Andrea Pellegrini, Joseph L. Greathouse, Valeria B...
ISCA
2012
IEEE
270views Hardware» more  ISCA 2012»
11 years 8 months ago
Revisiting hardware-assisted page walks for virtualized systems
Recent improvements in architectural supports for virtualization have extended traditional hardware page walkers to traverse nested page tables. However, current twodimensional (2...
Jeongseob Ahn, Seongwook Jin, Jaehyuk Huh