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ISLPED
1995
ACM
114views Hardware» more  ISLPED 1995»
13 years 9 months ago
Power and area optimization by reorganizing CMOS complex gate circuits
Thispaper proposes a method for achieving low-power control-logic modules using a combination of CMOS complex gate reorganization, transistor size optimization, and transistor lay...
M. Tachibana, S. Kurosawa, R. Nojima, Norman Kojim...
ISLPED
1995
ACM
96views Hardware» more  ISLPED 1995»
13 years 9 months ago
Towards a high-level power estimation capability
We will present a power estimation technique for digital integrated circuits that operates at the register transfer level RTL. Such a high-level power estimation capability is r...
Farid N. Najm
ISLPED
1995
ACM
193views Hardware» more  ISLPED 1995»
13 years 9 months ago
Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint
We consider the problem of transistor sizing in a static CMOS layout to minimizethe power consumption of the circuit subject to a given delay constraint. Based on our characteriza...
Manjit Borah, Robert Michael Owens, Mary Jane Irwi...
ISLPED
1995
ACM
95views Hardware» more  ISLPED 1995»
13 years 9 months ago
Reducing the frequency of tag compares for low power I-cache design
In current processors, the cache controller, which contains the cache directory and other logic such as tag comparators, is active for each instruction fetch and is responsible fo...
Ramesh Panwar, David A. Rennels
ISLPED
1995
ACM
112views Hardware» more  ISLPED 1995»
13 years 9 months ago
Ultra-low-power analog associative memory core using flash-EEPROM-based programmable capacitors
Analog techniques can lead to ultra-efficient computational systems when applied to the right applications. The problem of associative memory is well suited to array-based analog ...
Alan Kramer, Roberto Canegallo, Mauro Chinosi, D. ...