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ISLPED
2000
ACM
77views Hardware» more  ISLPED 2000»
13 years 9 months ago
A recursive algorithm for low-power memory partitioning
Memory-processor integration o ers new opportunities for reducing the energy of a system. In the case of embedded systems, one solution consists of mapping the most frequently acc...
Luca Benini, Alberto Macii, Massimo Poncino
ISLPED
2000
ACM
70views Hardware» more  ISLPED 2000»
13 years 9 months ago
An adaptive on-chip voltage regulation technique for low-power applications
In this paper we present a completely on-chip voltage regulation technique which promises to adjust the degree of voltage regulation in a digital logic chip in the face of process...
Nicola Dragone, Akshay Aggarwal, L. Richard Carley
ISLPED
2007
ACM
75views Hardware» more  ISLPED 2007»
13 years 6 months ago
Minimizing power dissipation during write operation to register files
This paper presents a power reduction mechanism for the write operation in register files (RegFiles), which adds a conditional charge-sharing structure to the pair of complementar...
Kimish Patel, Wonbok Lee, Massoud Pedram
ISLPED
2005
ACM
87views Hardware» more  ISLPED 2005»
13 years 11 months ago
Runtime identification of microprocessor energy saving opportunities
High power consumption and low energy efficiency have become significant impediments to future performance improvements in modern microprocessors. This paper contributes to the so...
W. L. Bircher, M. Valluri, J. Law, L. K. John
ISLPED
2003
ACM
91views Hardware» more  ISLPED 2003»
13 years 10 months ago
Reducing reorder buffer complexity through selective operand caching
Modern superscalar processors implement precise interrupts by using the Reorder Buffer (ROB). In some microarchitectures , such as the Intel P6, the ROB also serves as a repositor...
Gurhan Kucuk, Dmitry Ponomarev, Oguz Ergin, Kanad ...