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ISPASS
2006
IEEE
13 years 11 months ago
2006
IEEE
— Due to the long simulation times of the reference input sets, microarchitects resort to alternative techniques to speed up cycle-accurate simulations. However, the reduction in...
ISPASS
2006
IEEE
13 years 11 months ago
2006
IEEE
Modern processors attempt to overcome increasing memory latencies by anticipating future references and prefetching those blocks from memory. The behavior and possible negative si...
ISPASS
2006
IEEE
13 years 11 months ago
2006
IEEE
The present work presents a cycle-level execution-driven simulator for modern GPU architectures. We discuss the simulation model used for our GPU simulator, based in the concept o...
ISPASS
2006
IEEE
13 years 11 months ago
2006
IEEE
Applications in Computer Networks often require high throughput access to large data structures for lookup and classification. Many advanced algorithms exist to speed these searc...
ISPASS
2006
IEEE
13 years 11 months ago
2006
IEEE
The latest high-performance IBM PowerPC microprocessor, the POWER5 chip, poses challenges for performance model validation. The current stateof-the-art is to use simple hand-coded...