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ISPD
1999
ACM
94views Hardware» more  ISPD 1999»
14 years 3 months ago
Gate sizing with controlled displacement
- In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a path-based delay model to capture the timing c...
Wei Chen, Cheng-Ta Hsieh, Massoud Pedram
ISPD
1999
ACM
97views Hardware» more  ISPD 1999»
14 years 3 months ago
A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design
This paper presents a methodology to analyze signal integrity such as power voltage drop and clock skew in early stages of design, more specifically, when RTL-design and early flo...
Masato Iwabuchi, Noboru Sakamoto, Yasushi Sekine, ...
ISPD
1999
ACM
79views Hardware» more  ISPD 1999»
14 years 3 months ago
Partitioning with terminals: a "new" problem and new benchmarks
The presence of fixed terminals in hypergraph partitioning instances arising in top-down standard-cell placement makes such instances qualitatively different from the free hyperg...
Charles J. Alpert, Andrew E. Caldwell, Andrew B. K...
ISPD
1999
ACM
95views Hardware» more  ISPD 1999»
14 years 3 months ago
Incremental capacitance extraction and its application to iterative timing-driven detailed routing
In this paper, we consider delay optimization in multilayer detailed routing. Given a detailed routing by some detailed router, we iteratively improve the delays of critical nets ...
Yanhong Yuan, Prithviraj Banerjee
ISPD
1999
ACM
108views Hardware» more  ISPD 1999»
14 years 3 months ago
On the behavior of congestion minimization during placement
Typical placement objectives involve reducing net-cut cost or minimizing wirelength. Congestion minimization is least understood, however, it models routability accurately. In thi...
Maogang Wang, Majid Sarrafzadeh