- In this paper, we present an algorithm for gate sizing with controlled displacement to improve the overall circuit timing. We use a path-based delay model to capture the timing c...
This paper presents a methodology to analyze signal integrity such as power voltage drop and clock skew in early stages of design, more specifically, when RTL-design and early flo...
The presence of fixed terminals in hypergraph partitioning instances arising in top-down standard-cell placement makes such instances qualitatively different from the free hyperg...
Charles J. Alpert, Andrew E. Caldwell, Andrew B. K...
In this paper, we consider delay optimization in multilayer detailed routing. Given a detailed routing by some detailed router, we iteratively improve the delays of critical nets ...
Typical placement objectives involve reducing net-cut cost or minimizing wirelength. Congestion minimization is least understood, however, it models routability accurately. In thi...