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ISPD
2012
ACM
234views Hardware» more  ISPD 2012»
11 years 12 months ago
MAPLE: multilevel adaptive placement for mixed-size designs
We propose a new multilevel framework for large-scale placement called MAPLE that respects utilization constraints, handles movable macros and guides the transition between global...
Myung-Chul Kim, Natarajan Viswanathan, Charles J. ...
DAC
2012
ACM
11 years 6 months ago
ComPLx: A Competitive Primal-dual Lagrange Optimization for Global Placement
We develop a projected-subgradient primal-dual Lagrange optimization for global placement, that can be instantiated with a variety of interconnect models. It decomposes the origin...
Myung-Chul Kim, Igor L. Markov
ISPD
2012
ACM
288views Hardware» more  ISPD 2012»
11 years 12 months ago
Construction of realistic gate sizing benchmarks with known optimal solutions
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
Andrew B. Kahng, Seokhyeong Kang
ISPD
2012
ACM
248views Hardware» more  ISPD 2012»
11 years 12 months ago
A fast estimation of SRAM failure rate using probability collectives
Importance sampling is a popular approach to estimate rare event failures of SRAM cells. We propose to improve importance sampling by probability collectives. First, we use “Kul...
Fang Gong, Sina Basir-Kazeruni, Lara Dolecek, Lei ...
ISPD
2012
ACM
252views Hardware» more  ISPD 2012»
11 years 12 months ago
Towards layout-friendly high-level synthesis
There are two prominent problems with technology scaling: increasing design complexity and more challenges with interconnect design, including routability. High-level synthesis ha...
Jason Cong, Bin Liu 0006, Guojie Luo, Raghu Prabha...