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ISQED
2002
IEEE
175views Hardware» more  ISQED 2002»
13 years 10 months ago
On the Relation between SAT and BDDs for Equivalence Checking
State-of-the-art verification tools are based on efficient operations on Boolean formulas. Traditional manipulation techniques are based on Binary Decision Diagrams (BDDs) and SAT...
Sherief Reda, Rolf Drechsler, Alex Orailoglu
ISQED
2002
IEEE
83views Hardware» more  ISQED 2002»
13 years 10 months ago
A Hybrid BIST Architecture and Its Optimization for SoC Testing
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus
ISQED
2002
IEEE
85views Hardware» more  ISQED 2002»
13 years 10 months ago
Optimal Sequencing Energy Allocation for CMOS Integrated Systems
All synchronous CMOS integrated systems have to pay some sequencing overhead. This overhead includes the skew and the jitter of the clock. It also includes the setup time and the ...
Martin Saint-Laurent, Vojin G. Oklobdzija, Simon S...
ISQED
2002
IEEE
106views Hardware» more  ISQED 2002»
13 years 10 months ago
Trading off Reliability and Power-Consumption in Ultra-low Power Systems
Critical systems like pace-makers, defibrillators, wearable computers and other electronic gadgets have to be designed not only for reliability but also for ultra-low power consu...
Atul Maheshwari, Wayne Burleson, Russell Tessier
ISQED
2002
IEEE
203views Hardware» more  ISQED 2002»
13 years 10 months ago
Automatic Test Program Generation from RT-Level Microprocessor Descriptions
The paper addresses the issue of microprocessor and microcontroller testing, and follows an approach based on the generation of a test program. The proposed method relies on two p...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...