This paper discusses clock skew due to manufacturing variability and environmental change. In clock tree design, transition time constraint is an important design parameter that c...
As technology scales down, power supply noise is becoming a performance and reliability bottleneck in modern VLSI. We propose a power supply noise-aware design methodology for hig...
Multi-project wafer having several chips placed on the same reticle to lower mask cost is key to low-volume IC fabrication. In this paper1 , we proposed two MILP models for simult...
Double-Gate (DG) transistor has emerged as the most promising device for nano-scale circuit design. Independent control of front and back gate in DG devices can be effectively use...
Leakage power has become one of the most critical design concerns for the system-level chip designer. Multi-threshold techniques have been used to reduce runtime leakage power wit...