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ISQED
2005
IEEE
95views Hardware» more  ISQED 2005»
13 years 11 months ago
Statistical Analysis of Clock Skew Variation in H-Tree Structure
This paper discusses clock skew due to manufacturing variability and environmental change. In clock tree design, transition time constraint is an important design parameter that c...
Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi O...
ISQED
2005
IEEE
95views Hardware» more  ISQED 2005»
13 years 11 months ago
Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis
As technology scales down, power supply noise is becoming a performance and reliability bottleneck in modern VLSI. We propose a power supply noise-aware design methodology for hig...
Dongku Kang, Yiran Chen, Kaushik Roy
ISQED
2005
IEEE
76views Hardware» more  ISQED 2005»
13 years 11 months ago
Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers
Multi-project wafer having several chips placed on the same reticle to lower mask cost is key to low-volume IC fabrication. In this paper1 , we proposed two MILP models for simult...
Meng-Chiou Wu, Rung-Bin Lin
ISQED
2005
IEEE
64views Hardware» more  ISQED 2005»
13 years 11 months ago
Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET
Double-Gate (DG) transistor has emerged as the most promising device for nano-scale circuit design. Independent control of front and back gate in DG devices can be effectively use...
Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaush...
ISQED
2005
IEEE
87views Hardware» more  ISQED 2005»
13 years 11 months ago
A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology
Leakage power has become one of the most critical design concerns for the system-level chip designer. Multi-threshold techniques have been used to reduce runtime leakage power wit...
Puneet Gupta, Andrew B. Kahng, Puneet Sharma