Sciweavers

35 search results - page 6 / 7
» isqed 2006
Sort
View
ISQED
2006
IEEE
142views Hardware» more  ISQED 2006»
13 years 10 months ago
Constructing Current-Based Gate Models Based on Existing Timing Library
Current-based gate modeling achieves a new level of accuracy in nanoscale design timing and signal integrity analysis. However, to generate current-based gate models requires addi...
Andrew B. Kahng, Bao Liu, Xu Xu
ISQED
2006
IEEE
118views Hardware» more  ISQED 2006»
13 years 10 months ago
Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming
— In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linea...
Jeffrey Fan, I-Fan Liao, Sheldon X.-D. Tan, Yici C...
ISQED
2006
IEEE
118views Hardware» more  ISQED 2006»
13 years 10 months ago
Language-Based High Level Transaction Extraction on On-chip Buses
Abstract— With the increasing in silicon densities, SoC designs are the stream in modern electronics systems. Accordingly, the verification for SoC designs is crucial. One of th...
Yi-Le Huang, Chun-Yao Wang, Richard Yeh, Shih-Chie...
ISQED
2006
IEEE
108views Hardware» more  ISQED 2006»
13 years 10 months ago
SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching
This paper proposes a novel method for analyzing large onchip power delivery networks via a stochastic moment matching (SMM) method. The proposed method extends the existing direc...
Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan
ISQED
2006
IEEE
90views Hardware» more  ISQED 2006»
13 years 10 months ago
Transaction Level Error Susceptibility Model for Bus Based SoC Architectures
System on Chip architectures have traditionally relied upon bus based interconnect for their communication needs. However, increasing bus frequencies and the load on the bus calls...
Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykr...