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ISQED
2010
IEEE
117views Hardware» more  ISQED 2010»
13 years 11 months ago
Variation-aware speed binning of multi-core processors
John Sartori, Aashish Pant, Rakesh Kumar, Puneet G...
ISQED
2010
IEEE
170views Hardware» more  ISQED 2010»
13 years 6 months ago
New SRAM design using body bias technique for ultra low power applications
A new SRAM design is proposed. Body biasing improves the static noise margin (SNM) improved by at least 15% compared to the standard cells. Through using this technique, lowering ...
Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Yn...
ISQED
2010
IEEE
137views Hardware» more  ISQED 2010»
13 years 2 months ago
Analysis of power supply induced jitter in actively de-skewed multi-core systems
This paper studies multi-core clock distribution using active deskewing methods. We propose an efficient methodology that uses Verilog-A to model PLLs, clock trees and power suppl...
Derek Chan, Matthew R. Guthaus
ISQED
2010
IEEE
128views Hardware» more  ISQED 2010»
13 years 9 months ago
Soft error rate determination for nanoscale sequential logic
We analyze the neutron induced soft error rate (SER) by modeling induced error pulse using two parameters, occurrence frequency and probability density function for the pulse widt...
Fan Wang, Vishwani D. Agrawal
ISQED
2010
IEEE
161views Hardware» more  ISQED 2010»
13 years 6 months ago
Minimizing the power consumption of a Chip Multiprocessor under an average throughput constraint
- In a multi-core system, power and performance may be dynamically traded off by utilizing power management (PM). This paper addresses the problem of minimizing the total power con...
Mohammad Ghasemazar, Ehsan Pakbaznia, Massoud Pedr...