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ISSS
1995
IEEE
96views Hardware» more  ISSS 1995»
13 years 9 months ago
Time-constrained code compaction for DSPs
{DSP algorithms in most cases are subject to hard real-time constraints. In case of programmable DSP processors, meeting those constraints must be ensured by appropriate code gener...
Rainer Leupers, Peter Marwedel
ISSS
1995
IEEE
115views Hardware» more  ISSS 1995»
13 years 9 months ago
A system level design methodology for the optimization of heterogeneous multiprocessors
This paper presents a system level design methodology and its implementation as CAD tool for the optimization of heterogeneous multiprocessor systems. These heterogeneous systems,...
Markus Schwiegershausen, Peter Pirsch
ISSS
1995
IEEE
101views Hardware» more  ISSS 1995»
13 years 9 months ago
An approach to interface synthesis
This paper present a novel interface synthesis approach based on a one-sided interface description. Whereas most other approaches consider interface synthesis as optimizing a chan...
Jan Madsen, Bjarne Hald
ISSS
1995
IEEE
96views Hardware» more  ISSS 1995»
13 years 9 months ago
WWW based structuring of codesigns
This paper describes a codesign environment based on the WWW (World Wide Web) and its implementation. Tool invocations and their respective results are linked using hypertext docu...
Paul-Gerhard Plöger, Jörg Wilberg, Miche...
ISSS
1995
IEEE
98views Hardware» more  ISSS 1995»
13 years 9 months ago
On the use of VHDL-based behavioral synthesis for telecom ASIC design
higher levels of abstraction, due to the still increasing design complexities that can be expected in the near future. Behavioral synthesis can play a key role in this prospect, as...
Mark Genoe, Paul Vanoostende, Geert van Wauwe