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ISSS
2002
IEEE
103views Hardware» more  ISSS 2002»
13 years 10 months ago
A Symbolic Approach for the Combined Solution of Scheduling and Allocation
Scheduling is widely recognized as a very important step in highlevel synthesis. Nevertheless, it is usually done without taking into account the effects on the actual hardware im...
Luciano Lavagno, Mihai T. Lazarescu, Stefano Quer,...
ISSS
2002
IEEE
142views Hardware» more  ISSS 2002»
13 years 10 months ago
Round-Robin Arbiter Design and Generation
In this paper, we introduce a Round–robin Arbiter Generator (RAG) tool. The RAG tool can generate a design for a Bus Arbiter (BA). The BA is able to handle the exact number of b...
Vincent John Mooney III, George F. Riley, Eung S. ...
ISSS
2002
IEEE
154views Hardware» more  ISSS 2002»
13 years 10 months ago
Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops
Software pipelining and unfolding are commonly used techniques to increase parallelism for DSP applications. However, these techniques expand the code size of the application sign...
Bin Xiao, Zili Shao, Chantana Chantrapornchai, Edw...
ISSS
2002
IEEE
133views Hardware» more  ISSS 2002»
13 years 10 months ago
Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded Systems
This paper presents a novel low-energy memory design technique, considering effective bitwidth of variables for applicationspecific systems, called VAbM technique. It targets th...
Hiroto Yasuura, Hiroyuki Tomiyama, Takanori Okuma,...
ICCD
2002
IEEE
135views Hardware» more  ICCD 2002»
14 years 2 months ago
Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip
We present a co-simulation environment for multiprocessor architectures, that is based on SystemC and allows a transparent integration of instruction set simulators (ISSs) within ...
Luca Benini, Davide Bertozzi, Davide Bruni, Nicola...