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ISVLSI
2003
IEEE
118views VLSI» more  ISVLSI 2003»
9 years 7 months ago
Networks-On-Chip: The Quest for On-Chip Fault-Tolerant Communication
In this paper, we discuss the possibility of achieving onchip fault-tolerant communication based on a new communication paradigm called stochastic communication. Specifically, for...
Radu Marculescu
ISVLSI
2003
IEEE
115views VLSI» more  ISVLSI 2003»
9 years 7 months ago
Getting High-Performance Silicon from System-Level Design
System-level design techniques promise a way to lessen the productivity gap between fabrication and design. Unfortunately, these techniques have been slow to catch on, in part bec...
W. Rhett Davis
ISVLSI
2003
IEEE
86views VLSI» more  ISVLSI 2003»
9 years 7 months ago
Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOS
SOI (silicon-on-insulator) technology suffers from a number of floating body effects, most notably parasitic bipolar and history effects. These are influenced by the rapidly incre...
Koushik K. Das, Richard B. Brown
ISVLSI
2003
IEEE
157views VLSI» more  ISVLSI 2003»
9 years 7 months ago
Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering
This paper describes a technique for re-ordering of scan cells to minimize power dissipation that is also capable of reducing the area overhead of the circuit compared to a random...
Shalini Ghosh, Sugato Basu, Nur A. Touba
ISVLSI
2003
IEEE
138views VLSI» more  ISVLSI 2003»
9 years 7 months ago
Bouncing Threads: Merging a New Execution Model into a Nanotechnology Memory
The need for small, high speed, low power computers as the end of Moore’s law approaches is driving research into nanotechnology. These novel devices have significantly differe...
Sarah E. Frost, Arun Rodrigues, Charles A. Giefer,...
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