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    ITC
    2000
    IEEE
    55views Hardware» more  ITC 2000»
    Low power BIST design by hypergraph partitioning: methodology and architectures
    13 years 9 months ago
    Low power BIST design by hypergraph partitioning: methodology and architectures
    Download  dit.upc.es
    Patrick Girard, Christian Landrault, Loïs Gui...
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    ITC
    2000
    IEEE
    80views Hardware» more  ITC 2000»
    Test program synthesis for path delay faults in microprocessor cores
    13 years 9 months ago
    Test program synthesis for path delay faults in microprocessor cores
    Download  cadlab.ece.ucsb.edu
    Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng
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    ITC
    2000
    IEEE
    166views Hardware» more  ITC 2000»
    A built-in self-repair analyzer (CRESTA) for embedded DRAMs
    13 years 9 months ago
    A built-in self-repair analyzer (CRESTA) for embedded DRAMs
    Download  ic.ncue.edu.tw
    Tomoya Kawagoe, Jun Ohtani, Mitsutaka Niiro, Tukas...
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    ITC
    2000
    IEEE
    108views Hardware» more  ITC 2000»
    Computer-aided fault to defect mapping (CAFDM) for defect diagnosis
    13 years 9 months ago
    Computer-aided fault to defect mapping (CAFDM) for defect diagnosis
    Download  www.pld.ttu.ee
    Zoran Stanojevic, Hari Balachandran, D. M. H. Walk...
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    DT
    2000
    162views more  DT 2000»
    RT-Level ITC'99 Benchmarks and First ATPG Results
    13 years 5 months ago
    RT-Level ITC'99 Benchmarks and First ATPG Results
    Download  www.cercom.polito.it
    Effective high-level ATPG tools are increasingly needed, as an essential element in the quest for reducing as much as possible the designer work on gate-level descriptions. We pro...
    Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
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