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ITC
2000
IEEE
68views Hardware» more  ITC 2000»
13 years 10 months ago
Current ratios: a self-scaling technique for production IDDQ testing
The use of a single pass/fail threshold for IDDQ testing is unworkable as chip background currents increase to the point where they exceed many defect currents. This paper describ...
Peter C. Maxwell, Pete O'Neill, Robert C. Aitken, ...
ITC
2000
IEEE
84views Hardware» more  ITC 2000»
13 years 9 months ago
Non-intrusive BIST for systems-on-a-chip
1 The term "functional BIST" describes a test method to control functional modules so that they generate a deterministic test set, which targets structural faults within ...
Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wund...
ITC
2000
IEEE
101views Hardware» more  ITC 2000»
13 years 10 months ago
Reducing test data volume using external/LBIST hybrid test patterns
A common approachfor large industrial designs is to use logic built-in self-test (LBIST)followed by test data from an external tester. Because the fault coverage with LBIST alone ...
Debaleena Das, Nur A. Touba
ITC
2000
IEEE
110views Hardware» more  ITC 2000»
13 years 10 months ago
Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique
—This paper presents Algorithm-level REcomputing with Shifted Operands (ARESO), which is a new register transfer (RT) level time redundancy-based concurrent error detection (CED)...
Ramesh Karri, Kaijie Wu
ITC
2000
IEEE
101views Hardware» more  ITC 2000»
13 years 10 months ago
Which concurrent error detection scheme to choose ?
Concurrent error detection (CED) techniques (based on hardware duplication, parity codes, etc.) are widely used to enhance system dependability. All CED techniques introduce some ...
Subhasish Mitra, Edward J. McCluskey