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MICRO
2002
IEEE
143views Hardware» more  MICRO 2002»
13 years 10 months ago
Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor
Clustering is a common technique to overcome the wire delay problem incurred by the evolution of technology. Fully-distributed architectures, where the register file, the functio...
Enric Gibert, F. Jesús Sánchez, Anto...
MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
13 years 4 months ago
Generating physical addresses directly for saving instruction TLB energy
Power consumption and power density for the Translation Lookaside Buffer (TLB) are important considerations not only in its design, but can have a consequence on cache design as w...
Ismail Kadayif, Anand Sivasubramaniam, Mahmut T. K...
ISCA
2003
IEEE
89views Hardware» more  ISCA 2003»
13 years 10 months ago
MisSPECulation: Partial and Misleading Use of SPEC CPU2000 in Computer Architecture Conferences
A majority of the papers published in leading computer architecture conferences use SPEC CPU2000, or its predecessor SPEC CPU95, which has become the de facto standard for measuri...
Daniel Citron
ICRA
2002
IEEE
144views Robotics» more  ICRA 2002»
13 years 10 months ago
Sensing Nanonewton Level Forces by Visually Tracking Structural Deformations
When assembling MEMS devices or manipulating biological cells it is often beneficial to have information about the force that is being applied to these objects. This force informa...
Michael A. Greminger, Ge Yang, Bradley J. Nelson
NN
2002
Springer
119views Neural Networks» more  NN 2002»
13 years 4 months ago
Category regions as new geometrical concepts in Fuzzy-ART and Fuzzy-ARTMAP
In this paper we introduce novel geometric concepts, namely category regions, in the original framework of Fuzzy-ART (FA) and FuzzyARTMAP (FAM). The definitions of these regions a...
Georgios C. Anagnostopoulos, Michael Georgiopoulos