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MTDT
2003
IEEE
13 years 10 months ago
2003
IEEE
: Linked faults are very important for memory testing because they reduce the fault coverage of the tests. Their analysis has proven to be a source for new memory tests, characteri...
MTDT
2003
IEEE
13 years 10 months ago
2003
IEEE
Abstract: The high complexity of the faulty behavior observed in DRAMs is caused primarily by the presence of internal floating nodes in defective DRAMs. This paper describes a ne...
MTDT
2003
IEEE
13 years 10 months ago
2003
IEEE
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be ...
MTDT
2003
IEEE
13 years 10 months ago
2003
IEEE
ct Defect-based testing for digital logic concentrates primarily on methods of test application, including for example at-speed structural tests and IDDQ testing. In contrast, defe...
MTDT
2003
IEEE
13 years 10 months ago
2003
IEEE
Advances in System-on-Chip (SoC) technology rely on manufacturing and assembling high-performance system cores for many critical applications. Among these cores, memory occupies t...