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PATMOS
2004
Springer
13 years 10 months ago
2004
Springer
PATMOS
2004
Springer
13 years 10 months ago
2004
Springer
PATMOS
2004
Springer
13 years 10 months ago
2004
Springer
A full-adder implemented by combining branch-based logic and pass-gate logic is presented in this contribution. A comparison between this proposed full-adder (named BBL PT) and its...
PATMOS
2004
Springer
13 years 10 months ago
2004
Springer
Synchronization between independently clocked regions in a high performance system is often subject to latencies of more than one clock cycle. We show how the latency can be reduce...
PATMOS
2004
Springer
13 years 10 months ago
2004
Springer
The main result is the development, and delay comparison based on Logical Effort, of a number of high speed circuits for common arithmetic and related operations using threshold l...