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SBACPAD
2007
IEEE
554views Hardware» more  SBACPAD 2007»
10 years 10 months ago
Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors
Rafael Ubal, Julio Sahuquillo, Salvador Petit, Ped...
SBACPAD
2007
IEEE
121views Hardware» more  SBACPAD 2007»
10 years 10 months ago
DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement novel multithreaded execution models, like Scheduled DataFlow (SDF). This latter model pro...
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic
SBACPAD
2007
IEEE
130views Hardware» more  SBACPAD 2007»
10 years 10 months ago
Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)
In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-Multi Processor (CMP). It adopts a wormhole switc...
Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh
SBACPAD
2007
IEEE
91views Hardware» more  SBACPAD 2007»
10 years 10 months ago
Impacts of Multiprocessor Configurations on Workloads in Bioinformatics
Bioinformatics is among the most active research areas in computer science. In this study, we investigate a suite of workloads in bioinformatics on two multiprocessor systems with...
Youfeng Wu, Mauricio Breternitz Jr., Victor Ying
SBACPAD
2007
IEEE
128views Hardware» more  SBACPAD 2007»
10 years 10 months ago
Node Level Primitives for Parallel Exact Inference
We present node level primitives for parallel exact inference on an arbitrary Bayesian network. We explore the probability representation on each node of Bayesian networks and eac...
Yinglong Xia, Viktor K. Prasanna
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