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TCAD
2002
99views more  TCAD 2002»
13 years 4 months ago
Analysis of on-chip inductance effects for distributed RLC interconnects
This paper introduces an accurate analysis of on-chip inductance effects for distributed interconnects that takes the effect of both the series resistance and the output parasitic ...
Kaustav Banerjee, Amit Mehrotra
TCAD
2002
115views more  TCAD 2002»
13 years 4 months ago
Analytical models for crosstalk excitation and propagation in VLSI circuits
We develop a general methodology to analyze crosstalk effects that are likely to cause errors in deep submicron high speed circuits. We focus on crosstalk due to capacitive coupli...
Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer
TCAD
2002
107views more  TCAD 2002»
13 years 4 months ago
Value-sensitive automatic code specialization for embedded software
The objective of this work is to create a framework for the optimization of embedded software. We present algorithms and a tool flow to reduce the computational effort of programs,...
Eui-Young Chung, Luca Benini, Giovanni De Micheli,...
TCAD
2002
72views more  TCAD 2002»
13 years 4 months ago
Wire width planning for interconnect performance optimization
Abstract--In this paper, we study wire width planning for interconnect performance optimization in an interconnect-centric design flow. We first propose some simplified, yet near-o...
Jason Cong, David Zhigang Pan
TCAD
2002
73views more  TCAD 2002»
13 years 4 months ago
A timing-constrained simultaneous global routing algorithm
In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provi...
Jiang Hu, Sachin S. Sapatnekar