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TVLSI
2002
94views more  TVLSI 2002»
13 years 5 months ago
A network flow approach to memory bandwidth utilization in embedded DSP core processors
This paper presents a network flow approach to solving the register binding and allocation problem for multiword memory access DSP processors. In recently announced DSP processors,...
Catherine H. Gebotys
TVLSI
2002
102views more  TVLSI 2002»
13 years 5 months ago
Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique
Concurrent error detection (CED) based on time redundancy entails performing the normal computation and the re-computation at different times and then comparing their results. Time...
Ramesh Karri, Kaijie Wu
TVLSI
2002
102views more  TVLSI 2002»
13 years 5 months ago
Power-optimal encoding for a DRAM address bus
This paper presents an irredundant encoding technique to minimize the switching activity on a multiplexed Dynamic RAM (DRAM) address bus. The DRAM switching activity can be classif...
Wei-Chung Cheng, Massoud Pedram
TVLSI
2002
93views more  TVLSI 2002»
13 years 5 months ago
Simultaneous switching noise in on-chip CMOS power distribution networks
Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra lar...
Kevin T. Tang, Eby G. Friedman
TVLSI
2002
84views more  TVLSI 2002»
13 years 5 months ago
Application of instruction analysis/scheduling techniques to resource allocation of superscalar processors
This paper presents the development of instruction analysis/scheduling CAD techniques to measure the distribution of functional unit usage and the micro operation level parallelis...
Ing-Jer Huang, Ping-Huei Xie