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    VLSID
    1997
    IEEE
    119views VLSI» more  VLSID 1997»
    Channel and Switchbox Routing with Minimized Crosstalk - A Parallel Genetic Algorithm Approach
    13 years 8 months ago
    Channel and Switchbox Routing with Minimized Crosstalk - A Parallel Genetic Algorithm Approach
    Download  www.tu-dresden.de
    Jens Lienig
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    VLSID
    1997
    IEEE
    173views VLSI» more  VLSID 1997»
    Formal Verification of Digital Systems
    13 years 8 months ago
    Formal Verification of Digital Systems
    Download  www.math.fu-berlin.de
    Gitanjali Swamy
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    VLSID
    1997
    IEEE
    116views VLSI» more  VLSID 1997»
    Allocation of FIFO Structures in RTL Data Paths
    13 years 8 months ago
    Allocation of FIFO Structures in RTL Data Paths
    Download  www.cparity.com
    Heman Khanna, M. Balakrishnan
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    VLSID
    1997
    IEEE
    91views VLSI» more  VLSID 1997»
    Behavioral Array Mapping into Multiport Memories Targeting Low Power
    13 years 8 months ago
    Behavioral Array Mapping into Multiport Memories Targeting Low Power
    Download  www.scarpaz.com
    Preeti Ranjan Panda, Nikil D. Dutt
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    VLSID
    1997
    IEEE
    102views VLSI» more  VLSID 1997»
    Optimal Clock Period for Synthesized Data Paths
    13 years 8 months ago
    Optimal Clock Period for Synthesized Data Paths
    Download  ls12-www.cs.tu-dortmund.de
    A. R. Naseer, M. Balakrishnan, Anshul Kumar
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