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VLSID
2002
IEEE
122views VLSI» more  VLSID 2002»
14 years 4 months ago
IEEE 1394a_2000 Physical Layer ASIC
CN4011A is IEEE 1394a_2000 standard Compliant Physical Layer ASIC. It is a 0.18um mixed-signal ASIC incorporating three analog ports, PLL, reference generator for analog along wit...
Ranjit Yashwante, Bhalchandra Jahagirdar
VLSID
2000
IEEE
75views VLSI» more  VLSID 2000»
13 years 9 months ago
Timing Analysis with Implicitly Specified False Paths
We consider the problem of timing analysis in the presence of known false paths. The main difficulty in adaptation of classical breadth-first search to the problem is that at each...
Eugene Goldberg, Alexander Saldanha
VLSID
2000
IEEE
79views VLSI» more  VLSID 2000»
13 years 9 months ago
Inductive Noise Reduction at the Architectural Level
A methodology for reducing ground bounce in typical microprocessors and image processing architectures has been described. As we approach Gigascale Integration, chip power consump...
Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Viv...
VLSID
2000
IEEE
95views VLSI» more  VLSID 2000»
13 years 9 months ago
Hierarchical Error Diagnosis Targeting RTL Circuits
Diagnosis algorithms targeting design errors in RTL circuit descriptions are presented in this paper. The algorithms presented exploit the hierarchy available in RTL designs to lo...
Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee...
VLSID
2000
IEEE
121views VLSI» more  VLSID 2000»
13 years 9 months ago
Design of Synchronous Action Systems
The action systems framework has recently been applied to the area of synchronous VLSI design. In this paper, we present a set of concepts necessary in the formal design of synchr...
Juha Plosila, Tiberiu Seceleanu