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VLSID
2002
IEEE
75views VLSI» more  VLSID 2002»
14 years 4 months ago
Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts
Our target is automation of analog circuit's layout, which is a bottleneck in mixed-signal's design. We formulate the layout explicitly considering manufacturing process...
Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, M...
VLSID
2002
IEEE
109views VLSI» more  VLSID 2002»
14 years 4 months ago
Probabilistic Analysis of Rectilinear Steiner Trees
Steiner tree is a fundamental problem in the automatic interconnect optimization for VLSI design. We present a probabilistic analysis method for constructing rectilinear Steiner t...
Chunhong Chen
VLSID
2002
IEEE
94views VLSI» more  VLSID 2002»
14 years 4 months ago
Timing Yield Calculation Using an Impulse-Train Approach
This paper presents a new method to compute the probability distribution of the delay of a combinational circuit and uses it obtain an estimate of the yield of the process that ma...
Srinath R. Naidu
VLSID
2002
IEEE
149views VLSI» more  VLSID 2002»
14 years 4 months ago
Development of ASIC Chip-Set for High-End Network Processing Application-A Case Study
Choosing the right methodology is a significant step towards successful VLSI designs. Traditional methodologies and tools are no longer adequate to handle large and complex design...
Sanjeev Patel
VLSID
2002
IEEE
95views VLSI» more  VLSID 2002»
14 years 4 months ago
A Novel Method to Improve the Test Efficiency of VLSI Tests
This paper considers reducing the cost of test application by permuting test vectors to improve their defect coverage. Algorithms for test reordering are developed with the goal o...
Hailong Cui, Sharad C. Seth, Shashank K. Mehta