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VLSID
2006
IEEE
94views VLSI» more  VLSID 2006»
13 years 10 months ago
On the Size and Generation of Minimal N-Detection Tests
The main result of this paper, proved as a theorem, is that a lower bound on the number of test vectors that detect each fault at least N times is N
Kalyana R. Kantipudi
VLSID
2006
IEEE
130views VLSI» more  VLSID 2006»
14 years 5 months ago
A New Approach to Synthesize Multiple-Output Functions Using Reversible Programmable Logic Array
In this paper, a new realization for logic functions, namely Reversible Programmable Logic Array (RPLA), has been proposed. The proposed realization has the advantage of regularit...
Ahsan Raja Chowdhury, Rumana Nazmul, Hafiz Md. Has...
VLSID
2006
IEEE
144views VLSI» more  VLSID 2006»
14 years 5 months ago
A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm
In this paper we present a high-performance, high throughput, and area efficient architecture for the VLSI implementation of the AES algorithm. The subkeys, required for each round...
Naga M. Kosaraju, Murali R. Varanasi, Saraju P. Mo...
VLSID
2006
IEEE
170views VLSI» more  VLSID 2006»
14 years 5 months ago
16-Bit Segmented Type Current Steering DAC for Video Applications
In this paper, 16-bit, 50 MHz Current Steering DAC is designed. This DAC is implemented using TSMC 0.35 ?m technology. An optimum segmentation is done of 16-bits into binary and t...
Gaurav Raja, Basabi Bhaumik
VLSID
2006
IEEE
71views VLSI» more  VLSID 2006»
13 years 10 months ago
Clockless Pipelining for Coarse Grain Datapaths
In this paper, we present two novel synchronization approaches to support data flow in clockless designs using single-rail encoding. Both approaches are based on self-resetting st...
Abdelhalim Alsharqawi, Abdel Ejnioui