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VLSID
2006
IEEE
83views VLSI» more  VLSID 2006»
14 years 5 months ago
Parasitic Aware Routing Methodology Based on Higher Order RLCK Moment Metrics
In the multi-GHz frequency domain, inductive and capacitive parasitics of interconnects can cause significant 'ringing' or overdamping, which may lead to false switching...
Amitava Bhaduri, Ranga Vemuri
VLSID
2006
IEEE
153views VLSI» more  VLSID 2006»
14 years 5 months ago
An Asynchronous Interconnect Architecture for Device Security Enhancement
We present a new style of long-distance, on-chip interconnect, based loosely on the asynchronous GasP architecture. It has a number of advantages over conventional designs, the mo...
Simon Hollis, Simon W. Moore
VLSID
2006
IEEE
160views VLSI» more  VLSID 2006»
14 years 5 months ago
An Approach to Architectural Enhancement for Embedded Speech Applications
Advances in Human Computer Interaction(HCI) technology has resulted in widespread development of natural language and speech applications. These applications are known to be compu...
Soumyajit Dey, Susmit Biswas, Arijit Mukhopadhyay,...
VLSID
2006
IEEE
140views VLSI» more  VLSID 2006»
14 years 5 months ago
Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing
A low power multilevel interconnect architecture that uses wave-pipelined multiplexed (WPM) interconnect routing is proposed in this paper. WPM takes advantage of existing interco...
Ajay Joshi, Vinita V. Deodhar, Jeffrey A. Davis
VLSID
2006
IEEE
170views VLSI» more  VLSID 2006»
14 years 5 months ago
On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi Decoder
This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system. Multiple clock rates have ...
Koushik Maharatna, Alfonso Troya, Milos Krstic, Ec...