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VLSID
2009
IEEE
96views VLSI» more  VLSID 2009»
14 years 6 months ago
Efficient Placement of Compressed Code for Parallel Decompression
Code compression is important in embedded systems design since it reduces the code size (memory requirement) and thereby improves overall area, power and performance. Existing res...
Xiaoke Qin, Prabhat Mishra
VLSID
2009
IEEE
139views VLSI» more  VLSID 2009»
14 years 6 months ago
Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration
Increasing the number of cores in a multi-core processor reduces per-core performance. On the other hand, providing more resources to each core limits the number of cores on a chi...
Tameesh Suri, Aneesh Aggarwal
VLSID
2009
IEEE
115views VLSI» more  VLSID 2009»
14 years 6 months ago
Efficient Techniques for Directed Test Generation Using Incremental Satisfiability
Functional validation is a major bottleneck in the current SOC design methodology. While specification-based validation techniques have proposed several promising ideas, the time ...
Prabhat Mishra, Mingsong Chen
VLSID
2009
IEEE
99views VLSI» more  VLSID 2009»
14 years 6 months ago
Forecasting-Based Dynamic Virtual Channels Allocation for Power Optimization of Network-on-Chips
In this paper, we present a dynamic power management technique for optimizing the use of virtual channels in network on chips. The technique which is called dynamic virtual channe...
Amir-Mohammad Rahmani, Masoud Daneshtalab, Ali Afz...
VLSID
2009
IEEE
170views VLSI» more  VLSID 2009»
14 years 6 months ago
Code Transformations for TLB Power Reduction
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
Reiley Jeyapaul, Sandeep Marathe, Aviral Shrivasta...