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VTS
1995
IEEE
76views Hardware» more  VTS 1995»
13 years 8 months ago
Reliability evaluation of combinational logic circuits by symbolic simulation
Alessandro Bogliolo, Maurizio Damiani, Piero Olivo...
VTS
1995
IEEE
114views Hardware» more  VTS 1995»
13 years 8 months ago
A portable ATPG tool for parallel and distributed systems
Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo,...
VTS
1995
IEEE
80views Hardware» more  VTS 1995»
13 years 8 months ago
Improving topological ATPG with symbolic techniques
Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda,...
VTS
1995
IEEE
99views Hardware» more  VTS 1995»
13 years 8 months ago
Arithmetic built-in self test for high-level synthesis
In this paper, we propose an entirely new Built-In Self Test scheme for high-level synthesis of data path architectures that makes use of the arithmetic blocks in the data path to...
Nilanjan Mukherjee, H. Kassab, Janusz Rajski, Jerz...