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VTS
1997
IEEE
13 years 9 months ago
1997
IEEE
VTS
1997
IEEE
13 years 9 months ago
1997
IEEE
VTS
1997
IEEE
13 years 9 months ago
1997
IEEE
We describe a technique to generate critical hazard-free tests for self-timed control circuits build using a macromodule library, in a partial scan based DFT environment. Wepropos...
VTS
1997
IEEE
13 years 9 months ago
1997
IEEE
A new approach for testing the bistable elements (latches and flip-flops) in scan chain circuits is presented. In this approach, we generate test patterns that apply a checking ex...
VTS
1997
IEEE
13 years 9 months ago
1997
IEEE
Accumulators based on addition or subtraction can be used as test pattern generators. Some circuits, however, require long test lengths if the parameters of the accumulator are no...