25 search results - page 1 / 5 » vts 2005 |
VTS
2005
IEEE
13 years 10 months ago
2005
IEEE
VTS
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper presents a test architecture that addresses multiple problems faced in digital IC testing. These problems are test data volume, test application time, test power consum...
VTS
2005
IEEE
13 years 10 months ago
2005
IEEE
FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs, since SEUs in configuration bits of FPGAs result in permanent errors in the mapped...
VTS
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper describes a random jitter measurement technique using simple algorithms and comparator sampling. The approach facilitates using Automated Test Equipment (ATE) to valida...
VTS
2005
IEEE
13 years 10 months ago
2005
IEEE
Excessive power supply noise can lead to overkill during delay test. A static compaction algorithm is described in this paper that prevents such overkill. A power supply noise est...