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TVLSI
2008
164views more  TVLSI 2008»
9 years 10 months ago
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...
CODES
2003
IEEE
10 years 3 months ago
A modular simulation framework for architectural exploration of on-chip interconnection networks
Ever increasing complexity and heterogeneity of SoC platforms require diversiļ¬ed on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...
VLSID
2001
IEEE
200views VLSI» more  VLSID 2001»
10 years 11 months ago
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures
The emergence of several communication architectures for System-on-Chips provides designers with a variety of design alternatives. In addition, the need to customize the system ar...
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
DAC
2001
ACM
10 years 11 months ago
On-Chip Communication Architecture for OC-768 Network Processors
Faraydon Karim, Anh Nguyen, Sujit Dey, Ramesh R. R...
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