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DATE
2003
IEEE
132views Hardware» more  DATE 2003»
10 years 2 months ago
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip co...
Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung C...
DATE
2008
IEEE
126views Hardware» more  DATE 2008»
10 years 4 months ago
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs
In this paper, we use the generalized binary de Bruijn (GBDB) graph as a scalable and efficient network topology for an on-chip communication network. Using just two-layer wiring,...
Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimso...
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