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    IEEE
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    An accurate flip-flop selection technique for reducing logic SER
    13 years 6 months ago
    An accurate flip-flop selection technique for reducing logic SER
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    The combination of continued technology scaling and increased on-chip transistor densities has made vulnerability to radiation induced soft errors a significant design concern. In...
    Eric L. Hill, Mikko H. Lipasti, Kewal K. Saluja
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