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    Parallel-pipelined architecture for 2-D ICT VLSI implementation
    14 years 6 months ago
    Parallel-pipelined architecture for 2-D ICT VLSI implementation
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    The Integer Cosine Transform (ICT) has been shown to be an alternative to the DCT for image processing. This paper presents a parallel-pipelined architecture of an 8x8 ICT(10, 9, ...
    Juan A. Michell, Gustavo A. Ruiz, Angel M. Buron
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