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    ARVLSI
    1995
    IEEE
    146views VLSI» more  ARVLSI 1995»
    Array-of-arrays architecture for parallel floating point multiplication
    13 years 8 months ago
    Array-of-arrays architecture for parallel floating point multiplication
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    This paper presents a new architecture style for the design of a parallel floating point multiplier. The proposed architecture is a synergy of trees and arrays. Architectural mod...
    H. Dhanesha, K. Falakshahi, Mark Horowitz
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